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1 ? fn9199.2 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2005-2006. all rights reserved. r 3 technology? is a trademark of intersil americas inc. all other trademarks mentioned are the property of their respective owners. isl6262 two-phase core re gulator for imvp-6 mobile cpus the isl6262 is a two-phase buck converter regulator implementing intel? imvp-6 protocol, with embedded gate drivers. the two-phase buck converter uses two interleaved channels to effectively double the output voltage ripple frequency and thereby reduce output voltage ripple amplitude with fewer components, lower component cost, reduced power dissipation, and smaller real estate area. the heart of the isl6262 is r 3 technology?, intersil?s robust ripple regulator modulator. compared with the traditional multiphase buck regulator, the r 3 technology? has the fastest transient response. this is due to the r 3 modulator commanding variabl e switching frequency during a load transient. intel mobile voltage positioning (imvp) is a smart voltage regulation technology, which effectively reduces power dissipation in intel pentium processors. to boost battery life, the isl6262 supports dprslrvr (deeper sleep), dprstp# and psi# functions and maximizes the efficiency via automatically enabling diff erent phase operation modes. at heavy load operation of the active mode, the regulator commands the two phase continuous conduction mode (ccm) operation. while the psi# is asserted at the medium load in the active mode, the isl6262 smoothly disables one phase and operates in a one-phase ccm. when the cpu enters deeper sleep mode, the isl6262 enables diode emulation to maximize the efficiency at the light load. a 7-bit digital-to-analog converter (dac) allows dynamic adjustment of the core output vo ltage from 0.300v to 1.500v. a 0.5% system accuracy of t he core output voltage over temperature is achi eved by the isl6262. a unity-gain differential amplifier is provided for remote cpu die sensing. this allows the voltage on the cpu die to be accurately measured and re gulated per in tel imvp-6 specifications. current sensing can be realized using either lossless inductor dcr sensing or precision resistor sensing. a single ntc thermistor network thermally compensates the gain and the time constant of the dcr variations. features ? precision two-phase core voltage regulator - 0.5% system accuracy over temperature - enhanced load line accuracy ? internal gate driver with 2a driving capability ? dynamic phase adding/dropping ? microprocessor voltag e identification input - 7-bit vid input - 0.300v to 1.500v in 12.5mv steps - support vid change on-the-fly ? multiple current sensing schemes supported - lossless inductor dcr current sensing - precision resistive current sensing ? thermal monitor ? user programmable switching frequency ? differential remote cpu die voltage sensing ? static and dynamic current sharing ? overvoltage, undervoltage, and overcurrent protection ? pb-free plus anneal available (rohs compliant) ordering information part number part marking temp. (c) package pkg. dwg. # isl6262crz (note) isl6262crz -10 to 100 48 ld 7x7 qfn (pb-free) l48.7x7 isl6262crz-t (note) isl6262crz -10 to 100 48 ld 7x7 qfn (pb-free) l48.7x7 isl6262irz (note) isl6262irz -40 to 100 48 ld 7x7 qfn (pb-free) l48.7x7 ISL6262IRZ-T (note) isl6262irz -40 to 100 48 ld 7x7 qfn (pb-free) l48.7x7 note: intersil pb-free plus anneal products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. data sheet may 15, 2006
2 fn9199.2 may 15, 2006 pinout isl6262 (7x7 qfn) top view 3v3 clk_en# dprstp# dprslpvr 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 vr_on vid6 vid5 vid4 vid3 vid2 vid1 vid0 vdiff vsen rtn droop dfb vo vsum vin gnd vdd isen2 isen1 boot1 ugate1 phase1 pgnd1 lgate1 pvcc lgate2 pgnd2 phase2 ugate2 boot2 nc pgood psi# pgd_in rbias vr_tt# ntc soft ocset vw comp fb fb2 gnd pad (bottom) isl6262
3 fn9199.2 may 15, 2006 absolute maximum rati ngs thermal information supply voltage, vdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 -+7v battery voltage, vin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25v boot1,2 and ugate1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +30v all other pins. . . . . . . . . . . . . . . . . . . . . . . . -0.3v to (vdd +0.3v) open drain outputs, pgood, vr_tt# . . . . . . . . . . . . . . -0.3 -+7v recommended operating conditions supply voltage, vdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5v 5% battery voltage, vin. . . . . . . . . . . . . . . . . . . . . . . . . . . . +5v to 21v ambient temperature. . . . . . . . . . . . . . . . . . . . . . . . -10c to 100c junction temperature . . . . . . . . . . . . . . . . . . . . . . . -10c to 125c ambient temperature, industrial . . . . . . . . . . . . . . . -40c to 100c junction temperature, industrial . . . . . . . . . . . . . . . -40c to 125c thermal resistance (typical) ja c/w jc c/w qfn package (notes 1, 2). . . . . . . . . . 29 4.5 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . 150c maximum storage temperature range . . . . . . . . . . -65c to 150c maximum lead temperature (soldering 10s) . . . . . . . . . . . . 300c caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. ja is measured in free air with the component mounted on a high ef fective thermal conductivity te st board with ?direct attach? fe atures. see tech brief tb379. 2. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications v dd = 5v, t a = -40c to 100c, unless otherwise specified. parameter symbol test conditions min typ max units input power supply +5v supply current i vdd vr_on = 3.3v - 3.1 3.6 ma vr_on = 0v - - 1 a +3.3v supply current i 3v3 no load on clk_en# - - 1 a battery supply current at vin pin i vin vr_on = 0v, vin = 25v, - - 1 a por (power-on reset) threshold por r v dd rising - 4.35 4.5 v por f v dd falling 3.9 4.1 - v system and references system accuracy %error (v cc_core ) isl6262crz no load, closed loop, active mode, t a = 0c to 100c, vid = 0.75-1.5v -0.5 - 0.5 % vid = 0.5-0.7375v -8 - 8 mv vid = 0.3-0.4875v -15 - 15 mv %error (v cc_core ) isl6262irz t a = -40c to 100c, vid = 0.75-1.5v -0.8 - 0.8 % vid = 0.5-0.7375v -10 - 10 mv vid = 0.3-0.4875v -18 - 18 mv rbias voltage r rbias r rbias = 147k 1.45 1.47 1.49 v boot voltage v boot 1.188 1.2 1.212 v maximum output voltage v cc_core (max) vid = [0000000] - 1.5 - v v cc_core (min) vid = [1100000] - 0.3 - v vid off state vid = [1111111] - 0 - v channel frequency nominal channel frequency f sw r fset = 3.9k , 2 channel operation, v comp = 2v -300-khz adjustment range 200 - 500 khz isl6262
4 fn9199.2 may 15, 2006 amplifiers droop amplifier offset -0.3 - 0.3 mv error amp dc gain a v0 -90-db error amp gain-bandwidth product gbw c l = 20pf - 18 - mhz error amp slew rate sr c l = 20pf - 5 - v/s fb input current i in(fb) - 10 150 na isen imbalance voltage --1mv input bias current -20-na soft-start current soft-start current i ss -47 -41 -35 a soft geyserville current i gv |soft - ref|>100mv 170 200 230 a soft deeper sleep entry current i c4 dprslpvr = 3.3v -47 -41 -35 a soft deeper sleep exit current i c4ea dprslpvr = 3.3v 35 41 47 a soft deeper sleep exit current i c4eb dprslpvr = 0v 170 200 230 a gate driver driving capability ugate source resistance r src(ugate) 500ma source current - 1 1.5 ugate source current i src(ugate) v ugate_phase = 2.5v - 2 - a ugate sink resistance r snk(ugate) 500ma sink current - 1 1.5 ugate sink current i snk(ugate) v ugate_phase = 2.5v - 2 - a lgate source resistance r src(lgate) 500ma source current - 1 1.5 lgate source current i src(lgate) v lgate = 2.5v - 2 - a lgate sink resistance r snk(lgate) 500ma sink current - 0.5 0.9 lgate sink current i snk(lgate) v lgate = 2.5v - 4 - a ugate to phase resistance r p(ugate) -1.1-k gate driver switching timing (refer to timing diagram) ugate turn-on propagation delay t pdhu isl6262crz t a = -10c to 100c pv cc = 5v, outputs unloaded 20 30 44 ns t pdhu isl6262irz pv cc = 5v, outputs unloaded 18 30 44 ns lgate turn-on propagation delay t pdhl isl6262crz t a = -10c to 100c pv cc = 5v, outputs unloaded 71530ns t pdhl isl6262irz pv cc = 5v, outputs unloaded 5 15 30 ns bootstrap diode forward voltage v ddp = 5v, forward bias current = 2ma 0.43 0.58 0.72 v leakage v r = 16v - - 1 a power good and protection monitor pgood low voltage v ol i pgood = 4ma - 0.11 0.4 v pgood leakage current i oh p good = 3.3v -1 - 1 a electrical specifications v dd = 5v, t a = -40c to 100c, unless otherwise specified. (continued) parameter symbol test conditions min typ max units isl6262
5 fn9199.2 may 15, 2006 pgood delay t pgd isl6262crz t a = -10c to 100c clk_en# low to pgood high 5.5 6.8 8.1 ms t pgd isl6262irz clk_en# low to pgood high 5.3 6.8 8.1 ms overvoltage threshold o vh v o rising above setpoint > 1ms 160 200 240 mv severe overvoltage threshold o vhs v o rising above setpoint > 0.5s 1.675 1.7 1.725 v ocset reference current i(rbias) = 10a 9.8 10 10.2 a oc threshold offset droop rising above ocset > 120s -3.5 - 3.5 mv current imbalance threshold difference between isen1 and isen2 > 1ms - 7.5 - mv undervoltage threshold (vdiff-soft) uv f v o falling below setpoint for > 1ms -365 -300 -240 mv logic inputs vr_on, dprslpvr and pgd_in input low v il --1v vr_on, dprslpvr and pgd_in input high v ih 2.3 - - v leakage current of vr_on and pgd_in i il logic input is low -1 0 - a i ih logic input is high at 3.3v - 0 1 a leakage current of dprslpvr i il_dprslp dprslpvr input is low -1 0 - a i ih_dprslp dprslpvr input is high at 3.3v - 0.45 1 a dac(vid0-vid6), psi# and dprstp# input low v il --0.3v dac(vid0-vid6), psi# and dprstp# input high v ih 0.7 - - v leakage current of dac(vid0- vid6), psi# and dprstp# i il logic input is low -1 0 - a i ih logic input is high at 1v - 0.45 1 a thermal monitor ntc source current ntc = 1.3 v 53 60 68 a over-temperature threshold v(ntc) falling 1.165 1.18 1.205 v vr_tt# low output resistance r tt i = 20ma - 5 9 clk_en# output levels clk_en# high output voltage v oh 3v3 = 3.3v, i = -4ma 2.9 3.1 - v clk_en# low output voltage v ol i clk_en# = 4ma - 0.18 0.4 v electrical specifications v dd = 5v, t a = -40c to 100c, unless otherwise specified. (continued) parameter symbol test conditions min typ max units isl6262
6 fn9199.2 may 15, 2006 isl6262 gate driver timing diagram functional pin description pgood - power good open-drain output. will be pulled up externally by a 680 resistor to vccp or 1.9k to 3.3v. psi# - low load current indicator input. when asserted low, indicates a reduced load-current condition, and product goes into single phase operation. pgd_in - digital input. when asserted high, indicates vccp and vcc_mch voltages are within regulation. rbias - 147k resistor to vss se ts internal current reference. vr_tt# - thermal overload output indicator with open-drain output. over temperature pull-down resistance is 10 . ntc - thermistor input to vrtt# circuit and a 60a current source is connected internally to this pin. pwm ugate lgate 1v 1v t pdhl t rl t fu t ru t pdhu t fl 3v3 clk_en# dprstp# dprslpvr 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 vr_on vid6 vid5 vid4 vid3 vid2 vid1 vid0 vdiff vsen rtn droop dfb vo vsum vin gnd vdd isen2 isen1 boot1 ugate1 phase1 pgnd1 lgate1 pvcc lgate2 pgnd2 phase2 ugate2 boot2 nc pgood psi# pgd_in rbias vr_tt# ntc soft ocset vw comp fb fb2 gnd pad (bottom) isl6262
7 fn9199.2 may 15, 2006 soft - a capacitor from this pin to gnd pin sets the maximum slew rate of the output voltage. the soft pin is the non-inverting input of the error amplifier. ocset - overcurrent set input. a resistor from this pin to vo sets droop voltage limit for oc trip. a 10a current source is connected internally to this pin. vw - a resistor from this pin to comp programs the switching frequency (exa. 4.42k ? 300khz). comp - this pin is the output of the error amplifier. fb - this pin is the inverting input of error amplifier. fb2 - there is a switch between fb2 pin and the fb pin. the switch is closed in single-phase operation and is opened in two phase operation. the components connecting to fb2 is to adjust the compensation in single phase operation to achieve optimum performance. vdiff - this pin is the output of the differential amplifier. vsen - remote core voltage sense input. rtn - remote core voltage sense return. droop - output of the droop ampl ifier. the voltage level on this pin is the sum of vo and the programmed droop voltage by the external resistors. dfb - inverting input to droop amplifier. vo - an input to the ic that reports the local output voltage. vsum - this pin is connected to the summation junction of channel current sensing. vin - battery supply voltage. it is used for input voltage feedforward to improve the in put line transient performance. vss - signal ground. connect to local controller ground. vdd - 5v control power supply. isen2 - individual current sharing sensing for channel 2. isen1 - individual current sharing sensing for channel 1. n/c - not connected. grounding this pin to signal ground in the practical layout. boot2 - this pin is the upper gate driver supply voltage for phase 2. an internal boot strap diode is connected to the pvcc pin. ugate2 - upper mosfet gate signal for phase 2. phase2 - the phase node of phase 2. this pin should connect to the source of upper mosfet. pgnd2 - the return path of the lower gate driver for phase 2. lgate2 - lower-side mosfet gate signal for phase 2. pvcc - 5v power supply for gate drivers. lgate1 - lower-side mosfet gate signal for phase 1. pgnd1 - the return path of the lower gate driver for phase 1. phase1 - the phase node of phase 1. this pin should connect to the source of upper mosfet. ugate1 - upper mosfet gate signal for phase 1. boot1 - this pin is the upper gate driver supply voltage for phase 1. an internal boot stra p diode is connected to the pvcc pin. vid0, vid1, vid2, vid3, vid4, vid5, vid6 - vid input with vid0 is the least significant bit (lsb) and vid6 is the most significant bit (msb). vr_on - digital input enable. a high level logic signal on this pin enables the regulator. dprslpvr - deeper sleep enable signal. a high level logic indicates the micro-processor is in deeper sleep mode and also indicates a slow c4 entry or exit rate with 41a discharging or charging the soft cap. dprstp# - deeper sleep slow wake up signal. a low level logic signal on this pin indicates the micro-processor is in deeper sleep mode. clk_en# - digital output for system pll clock. goes active 10s after pgd_in is active and vcore is within 10% of boot voltage. 3v3 - 3.3v supply voltage for clk_en#. isl6262
8 fn9199.2 may 15, 2006 functional block diagram 1 + - dac gnd comp vid0 vid1 vid2 vid3 vid4 soft mode control soft vr_on vin vid5 fb e/a + - pgood pgood monitor and logic rtn modulator modulator vin vsoft vin phase control logic psi# dprslpvr current balance vw phase sequencer isen1 vo vin flt rbias vdd isen2 vsum dfb vo droop + - vo vdiff vsen oc i_balf pgd_in dacout clk_en# ocset + - ntc vr_tt# 54a 1 + - + + oc vin vsoft oc 1.2v droop vid6 10a vo phase1 driver logic pvcc lgate1 ugate1 boot1 pgnd1 phase2 driver logic pvcc lgate2 ugate2 boot2 pgnd2 flt pvcc vsoft dprstp# single phase fb2 3v3 pvcc pvcc pvcc ultra- sonic timer mode change request 0.5 + - single phase vw vw ch1 ch2 ch1 ch2 p good flt fault and pgood logic 6a 1.18v figure 1. simplified function block diagram of isl6262 single phase isl6262
9 fn9199.2 may 15, 2006 typical performance curves 300khz, dcr sense, 2xirf7 821/2xirf7832 per phase figure 2. active mode efficiency, 2 phase, ccm, psi# = high, vid = 1.15v figure 3. active mode load line, 2 phase, ccm, psi# = high, vid = 1.15v figure 4. active mode efficiency, 1 phase, ccm, psi# = low, vid = 1.15v figure 5. active mode load line, 1 phase, ccm, psi# = low, vid = 1.15v figure 6. deeper sleep mode efficiency, 1 phase, dcm mode, vid = 0.7625v figure 7. deeper sleep mode load line, 1 phase, dcm mode, vid = 0.7625v 0 5 10 15 20 25 30 35 40 45 50 i out (a) 0 10 20 30 40 50 60 70 80 90 100 efficiency (%) v in = 8.0v v in = 12.6v v in = 19.0v 0 1020304050 i out (a) 1.02 1.04 1.06 1.08 1.10 1.14 1.16 v out (v) v in = 8.0v v in = 12.6v v in = 19.0v 1.12 02468101214161820 i out (a) 0 10 20 30 40 50 60 70 80 90 100 efficiency (%) v in = 8.0v v in = 19.0v v in = 12.6v 0 4 6 8 10 20 i out (a) 1.10 1.11 1.12 1.13 1.14 1.15 1.16 v out (v) v in = 8.0v 2 12141618 v in = 12.6v v in = 19.0v 0.1 1 10 i out (a) 50 60 70 80 90 100 efficiency (%) v in = 12.6v v in = 8.0v v in = 19.0v 024 6810 i out (a) 0.735 0.74 0.745 0.75 0.755 0.765 v out (v) v in = 8.0v 0.76 v in = 19.0v v in = 12.6v isl6262
10 fn9199.2 may 15, 2006 typical performance curves 0.36h filter inductor and 4 x 330f output sp caps figure 8. soft-start waveform showing slew rate of 2.5mv/s at vid = 1v, i load = 10a figure 9. soft-start waveform showing slew rate of 2.5mv/s at vid = 1.4375v, i load = 10a figure 10. soft-start waveform showing clk_en# and imvp-6 pgood figure 11. inrush current at start-up, v in = 8v, vid = 1.4375v, i load = 10a figure 12. 8v-20v input line transient response, c in = 240f figure 13. 2 phase current balance, full load = 50a v out v soft vr_on c soft = 15nf vr_on v out v soft c soft = 15nf v out @ 1.4375v v out @ 1.2v pgd_in clk_en# imvp-6_pwrgd i in il1, il2 v out i in line transient v out v in isl6262
11 fn9199.2 may 15, 2006 figure 14. load step-up response via cpu socket mpga479, 35a load step @ 200a/s, 2 phase ccm figure 15. vid3 change of 010x000 from 1.v to 1.1v at dprslpvr = 0, dprstp# = 1, psi# = 1 figure 16. load dump response via cpu socket mpga479, 35a load step @ 200a/s, 2 phase ccm figure 17. vid3 change of 010x000 from 1.1v to 1v at dprslpvr = 0, dprstp# = 1, psi# = 1 figure 18. 2-ccm to 1-ccm upon psi# assertion with vid lsb change, at dprslpvr = 0, dprstp# = 1, i load = 10a figure 19. 1-ccm to 2-ccm upon psi# deassertion with vid lsb change at dprslpvr = 0, dprstp# = 1 typical performance curves 0.36h filter inductor and 4 x 330f output sp caps (continued) v out load transient dynamic vid active mode phase1, phase2 vid3 v out v out load transient dynamic vid active mode phase1, phase2 vid3 v out drop phase in active mode psi# phase1 phase2 v core add phase in active mode psi# phase2 phase1 v core isl6262
12 fn9199.2 may 15, 2006 figure 20. c4 enter with vid change 0011x00 from 1.2v to 1.15v, i load = 2a, transition of 2-ccm to 1-dcm, psi# toggle from 1 to 0 with dprslpvr from 0 to 1 figure 21. vid3 change of 010x000 from 1.v to 1.1v at dprslpvr = 0, dprstp# = 1, psi# = 1 figure 22. fast break c4 exit at load = 0.1a figure 23. c4 entry with vid change of 011x011 from 0.8625v to 0.7625v, i load = 3a, 1-ccm to 1-dcm figure 24. overcurrent protection figure 25. 1.7v overvoltage protection shows output voltage pulled low to 0.9v and pwm three-state typical performance curves 0.36h filter inductor and 4 x 330f output sp caps (continued) c4 entry with psi# assertion phase1 phase2 v out dprslpvr c4 exit/phase add phase1 phase2 v out dprslpvr fast break c4 exit phase1 phase2 v out dprslpvr c4 entry with psi# = 0 phase1 phase2 v out dprslpvr il1, il2 v out pgood phase1 v out pgood isl6262
13 fn9199.2 may 15, 2006 simplified applicat ion circuit for dcr current sensing figure 26. isl6262 based two-phase buck converter with inductor dcr current sensing r 2 r 1 v o c 1 c 2 v +5 vid<0:6> dprslpvr vr_on c o soft vdiff ocset fb psi# rbias vw vo comp vids dprslpvr pgd_in vin vr_on gnd pgood vdd rtn r n c cs vr_tt# vsum r fset psi# remote sense isen2 vsen clk_en# mchok clk_enable# vr_tt# ntc isl6262 imvp-6_pwrgd ugate1 lgate1 phase1 boot1 v in droop dfb l o r l c l vsum isen2 vo' vo' vsum pgnd2 isen1 v in l o r l c l vsum isen1 vo' ugate2 lgate2 phase2 boot2 pvcc pgnd2 dprstp# fb2 r 3 c 3 3v3 v +3.3 r 5 r 4 c 4 r 6 dprstp# r 7 r 11 r 9 r 10 r 8 r 13 r 12 c 5 c 6 c 8 c 7 c 8 c 9 ntc v in network isl6262
14 fn9199.2 may 15, 2006 simplified applicati on circuit for resist ive current sensing figure 27. isl6262 based two-phase buck converter with resistive current sensing r 2 r 1 v o c 1 c 2 v +5 vid<0:6> dprslpvr vr_on c o soft vdiff ocset fb psi# rbias vw vo comp vids dprslpvr pgd_in vin vr_on gnd pgood vdd rtn c hf vr_tt# vsum r fset psi# remote sense isen2 vsen clk_en# mchok clk_enable# vr_tt# ntc isl6262 imvp-6_pwrgd ugate1 lgate1 phase1 boot1 v in droop dfb r l c l vsum isen2 vo' vo' vsum pgnd2 isen1 v in l r l c l vsum isen2 vo' ugate2 lgate2 phase2 boot2 pvcc pgnd2 dprstp# fb2 r 3 c 3 3v3 v +3.3 r 5 r 4 c 4 r 6 dprstp# r 7 r 11 r 9 r 10 r 8 r 12 r 11 c 5 c 6 c 8 c 7 c 9 c 9 v in r s l r s isl6262
15 fn9199.2 may 15, 2006 theory of operation the isl6262 is a two-phase regulator implementing intel? imvp-6 protocol and includes embedded gate drivers for reduced system cost and board area. the regulator provides optimum steady-state and transient performance for microprocessor core applications up to 50a. system efficiency is enhanced by idling one phase at low-current and implementing automatic dcm-mode operation. the heart of the isl6262 is r 3 technology?, intersil?s robust ripple regulator modulator. the r 3 modulator combines the best features of fixed frequency pwm and hysteretic pwm while elim inating many of their shortcomings. the isl6262 modulator internally synthesizes an analog of the inductor ripple current and uses hysteretic comparators on those signals to establish pwm pulse widths. operating on these large-amplitude, noise-free synthesized signals allows the isl6262 to achieve lower output ripple and lower phase jitter than either conventional hysteretic or fixed frequency pwm controllers. unlike conventional hysteretic converters, the isl6262 has an error amplifier that allows the controll er to maintain a 0.5% voltage regulation accuracy throughout the vid range from 0.75v to 1.5v. the hysteresis window voltage is relative to the error amplifier output such that load current transients results in increased switching frequency, which gives the r 3 regulator a faster response than conventional fixed frequency pwm controllers. transient load cu rrent is inherently shared between active phases due to the use of a common hysteretic window voltage. individual average phase voltages are monitored and controlled to equally share the static current among the active phases. start-up timing with the controller's +5v vdd voltage above the por threshold, the start-up sequence begins when vr_on exceeds the 3.3v logic high threshold. approximately 100s later, soft and vout begin ramping to the boot voltage of 1.2v. at start-up, t he regulator always operates in a 2-phase ccm mode, regardless of control signal assertion levels. during this internal, the soft cap is charged by 41a current source. if the soft capacitor is selected to be 20nf, the soft ramp will be at 2mv/s for a soft-start time of 600s. once vout is within 10% of the boot voltage and pgd_in is high for six pwm cycles (20s for frequency = 300khz), then clk_ en# is pulled low and the soft cap is charged/discharged by approximate 200a. therefore, vout slews at +10m v/s to the voltage set by the vid pins. approximately 7ms later, pgood is asserted high. typical start-up timing is shown in figure 28. pgd_in latch it should be noted that pgd_in going low will cause the converter to latch off. this state will be cleared when vr_on is toggled. this feature allows the converter to respond to other system voltage outages immediately. static operation after the start sequence, the output voltage will be regulated to the value set by the vid inputs per table 1. the entire vid table is presented in the intel imvp-6 specification. the isl6262 will control the no-load output voltage to an accuracy of 0.5% over the range of 0.75v to 1.5v. a fully-differential amplifier implements core voltage sensing for precise voltage control at the microprocessor die. the inputs to the amplifier ar e the vsen and rtn pins. as the load current increases from zero, the output voltage will droop from the vid table value by an amount proportional to current to achieve the imvp-6 load line. the isl6262 provides for current to be measured using either resistors in series with the cha nnel inductors as shown in the application circuit of figure 27, or using the intrinsic series table 1. truncated vid table for intel imvp-6 specification vid6 vid5 vid4 vid3 vid2 vid1 vid0 vout (v) 00000001. 5000 00000011. 4875 00001011. 4375 00100011. 2875 00111001.15 01101010. 8375 01110110. 7625 11000000. 3000 11111110. 0000 figure 28. soft-start waveforms using a 20nf soft capacitor v dd vr_on 100s soft & vo pgd_in clk_en# imvp-6 pgood 6.8ms 20s vboot vid commanded voltage 10mv/s 2mv/s isl6262
16 fn9199.2 may 15, 2006 resistance of the inductors as shown in the application circuit of figure 26. in both cases signals representing the inductor currents are summed at vsum, which is the non-inverting input to the droop amplifier shown in the block diagram of figure 1. the voltage at th e droop pin minus the output voltage, vo, is a high-bandwidth analog of the total inductor current. this voltage is used as an input to a differential amplifier to achieve the imvp-6 load line, and also as the input to the overcurrent protection circuit. when using inductor dcr current sensing, a single ntc element is used to compensate the positive temperature coefficient of the copper winding thus maintaining the load- line accuracy. in addition to monitoring the total current (used for droop and overcurrent protection), the individual channel average currents are also monitored and used for balancing the load between channels. the ibal circuit will adjust the channel pulse-widths up or down relative to the other channel to cause the voltages presented at the isen pins to be equal. the isl6262 controller can be configured for two-channel operation, with the channels oper ating 180 degrees apart. the channel pwm frequency is determined by the value of r fset connected to pin vw as shown in figure 26 and figure 27. input and output ripple frequencies will be the channel pwm frequency multiplied by the number of active channels. high efficiency operation mode the isl6262 has several operating modes to optimize efficiency. the controller's operational modes are designed to work in conjunction with the intel imvp-6 control signals to maintain the optimal system configuration for all imvp-6 conditions. these operating modes are established by the imvp-6 control signal inputs such as psi#, dprslpvr, and dprstp# as shown in table 2. at high current levels, the system will operate with both phases fully active, responding rapidly to transients and deliver the maximum power to the load. at reduced load current levels, one of the phases may be idled. this configuration will minimize switching losses, while still maintaining transient response capability. at the lowest current levels, the contro ller automatically configures the system to operate in single-phase au tomatic-dcm mode, thus achieving the highest possible efficiency. in this mode of operation, the lower fet will be configured to automatically detect and prevent discharge current flowing from the output capacitor through the inductors, and the switching frequency will be pr oportionately reduced, thus greatly reducing both conduction and switching losses. smooth mode transitions ar e facilitated by the r 3 technology?, which correctly maintains the internally synthesized ripple currents throughout mode transitions. the controller is thus able to deliv er the appropriate current to the load throughout mode transition s. the controller contains embedded mode-transition al gorithms which robustly maintain voltage-regulation for all control signal input sequences and durations. mode-transition sequences will often occur in concert with vid changes; therefore the timing of the mode transitions of isl6262 has been carefully designed to work in concert with vid changes. for example, transitions into single-phase mode will be delayed until the vid induced voltage ramp is complete, to allow the associated output capacitor charging current is shared by both inductor paths. while in single- phase automatic-dcm mode, vid changes will initiate an immediate return to two-phase ccm mode. this ensures that both inductor paths share the output capacitor charging current and are fully active for the subsequent load current increases. the controller contains internal counters which prevent spurious control signal glitches from resulting in unwanted mode transitions. control signals of less than two switching periods do not result in phase-idling. signals of less than 7 switching periods do not re sult in implementation of automatic-dcm mode. table 2. control signal truth tabl es for operation modes of isl6262 dprslpvr dprstp# psi# phase operation modes expected cpu mode intel imvp-6 compliant logic 0 1 1 2-phase ccm active mode 0 1 0 1-phase ccm active mode 1 0 1 1-phase diode emulation deeper sleep mode 1 0 0 1-phase diode emulation deeper sleep mode other logic commands 0 0 1 2-phase ccm 0 0 0 1-phase ccm 1 1 1 2-phase ccm 1 1 0 1-phase ccm isl6262
17 fn9199.2 may 15, 2006 while transitioning to single-phase operation, the controller smoothly transitions current from the idling-phase to the active-phase, and detects the idling-phase zero-current condition. during transitions into automatic-dcm or forced- ccm mode, the timing is carefully adjusted to eliminate output voltage excursions. when a phase is added, the current balance between phases is quickly restored. while psi# is high, both phases are switching. if psi# is asserted low and either dprstp# or dprslpvr are not asserted, the controller will tran sition to ccm operation with only phase 1 switching, and both fet's of phase 2 will be off. the controller will thus eliminate switching losses associated with the unneeded channel. when psi#, dprstp#, and dprslpvr are all asserted, the controller will transition to single-phase dcm mode. in this mode, both fet's associated with phase 2 will be off, and the isl6262 will turn-off the lower fet of channel 1 whenever the channel 1 current decays to zero. as load is further reduced, the phase 1 channel switching frequency will decrease, thus maintaining high efficiency. dynamic operation refer to figure 29, the isl6262 responds to changes in vid command voltage by slewing to new voltages with a dv/dt set by the soft capacitor and by the state of dprslpvr. with c soft = 15nf and dprslpvr high, the output voltage will move at 2.8mv/s for large changes in voltage. for dprslpvr low, the large signal dv/dt will be 13mv/s. as the output vo ltage approaches the vid command value, the dv/dt moderates to prevent overshoot. keeping dprslpvr high for voltage transitions into and out of deeper sleep will result in low dv/dt output voltage changes with resulting minimized audio noise. for fastest recovery from deeper sleep to active mode, holding dprslpvr low will result in maximum dv/dt. therefore, the isl6262 is imvp-6 compliant for dprstp# and dprslpvr logic. intersil's r 3 technology? has intrinsic voltage feedforward. as a result, high-speed input voltage steps do not result in significant output voltage perturbations. in response to load current step increases, the isl6262 will transiently raise the switching frequency so that response time is decreased and current is shared by two channels. protection the isl6262 provides overcurrent, overvoltage, under- voltage protection and over-temperature protection as shown in table 3. figure 29. deeper sleep transition showing dprslpvr's effect on exit slew rate vid # v out & v soft dprslpvr -2.5mv/s 2.5mv/s 10mv/s table 3. fault-protection summary of isl6262 fault duration prior to protection protection actions fault reset overcurrent fault 120s pwm1, pwm2 three-state, pgood latched low vr_on toggle or vdd toggle way-overcurrent fault <2s pwm1, pwm2 three-state, pgood latched low vr_on toggle or vdd toggle overvoltage fault (1.7v) immediately low-side fet on until vcore <0.85v, then pwm three-state, pgood latched low (ov-1.7v always) vdd toggle overvoltage fault (+200mv) 1ms pwm1, pwm2 three-state, pgood latched low vr_on toggle or vdd toggle undervoltage fault (-300mv) 1ms pwm1, pwm2 three-state, pgood latched low vr_on toggle or vdd toggle unbalance fault (7.5mv) 1ms pwm1, pwm2 three-state, pgood latched low vr_on toggle or vdd toggle over-temperature fault (ntc <1.18v) immediately vr_tt# goes low n/a isl6262
18 fn9199.2 may 15, 2006 overcurrent protection is tied to the voltage droop which is determined by the resistors selected as described in the ?component selection and application? section. after the load-line is set, the ocset re sistor can be selected to detect overcurrent at any le vel of droop voltage. an overcurrent fault will occur when the load current exceeds the overcurrent setpoint voltage while the regulator is in a 2-phase mode. while the regulator is in a 1-phase mode of operation, the overcurrent setpoi nt is automatically reduced by half. for overcurrents less than twice the ocset level, the over-load condition must exist for 120s in order to trip the oc fault latch. this is shown in figure 24. for over-loads exceeding twice the set level, the pwm outputs will immediately shut off and pgood will go low to maximize protection due to hard shorts. in addition, excessive phase unbalance, for example, due to gate driver failure, will be dete cted in two-phase operation and the controller will be shut-down after one millisecond's detection of the excessive phase current unbalance. the phase unbalance is detected by the voltage on the isen pins if the difference is greater than 7.5mv. undervoltage protection is independent of the overcurrent limit. if the output voltage is less than the vid set value by 300mv or more, a fault will latch after one millisecond in that condition. the pwm outputs wil l turn off and pgood will go low. note that most practical core regulators will have the overcurrent set to trip before the -300mv undervoltage limit. there are two levels of overvo ltage protection and response. for output voltage exceeding the set value by +200mv for one millisecond, a fault is decla red. all of the above faults have the same action taken: pgood is latched low and the upper and lower power fets are turned off so that inductor current will decay through the fet body diodes. this condition can be reset by bringing vr_on low or by bringing vdd below 4v. when these inputs are returned to their high operating levels, a soft-start will occur. refer to figure 25, the second level of overvoltage protection behaves differently. if the output exceeds 1.7v, an ov fault is immediately declared, pgood is latched low and the low-side fets are turned on. the low-side fets will remain on until the output voltage is pulled down below about 0.85v at which time all fets are turned off. if the output again rises above 1.7v, the protection process is repeated. this offers the maximum amount of protection against a shorted high-side fet while preventing output ringing below ground. the 1.7v ov is not reset with vr_on, but requires that vdd be lowered to reset. the 1.7v ov detector is active at all times that the controller is enabled including after one of the other faults occurs so that the processor is protected agains t high-side fet leakage while the fets are commanded off. the isl6262 has a thermal throttling feature. if the voltage on the ntc pin goes below t he 1.18v over-temperature threshold, the vr_tt# pin is pulled low indicating the need for thermal throttling to the syst em oversight processor. no other action is taken within the isl6262 in response to ntc pin voltage. component selectio n and application soft-start and mode change slew rates the isl6262 uses 2 slew rates for various modes of operation. the first is a slow slew rate, used to reduce inrush current during start-up. it is also used to reduce audible noise when entering or exitin g deeper sleep mode. a faster slew rate is used to exit out of deeper sleep and to enhance system performance by achieving active mode regulation more quickly. note that the soft cap current is bidirectional. the current is flowing into the soft capacitor when the output voltage is commanded to rise, and out of the soft capacitor when the output voltage is commanded to fall. refer to figure 30. the two slew rates are determined by commanding one of two current sources onto the soft pin. as can be seen in figure 30, the soft pin has a capacitance to ground. also, the soft pin is the input to the error amplifier and is, ther efore, the commanded system voltage. depending on the state of the system, i.e. start-up or active mode, and the state of the dprslpvr pin, one of the two currents shown in figure 30 will be used to charge or discharge this capacitor, thereby controlling the slew rate of the commanded voltage. these currents can be found under the soft-start current section of the electrical specification table. the first current, labelled i ss , is given in the specification table as 41a. this current is used during soft-start. the second current, i 2 sums with i ss to get the larger of the two currents, labeled i gv in the electrical specification table. this total current is typically 200a with a minimum of 175a. the imvp-6 specification re veals the critical timing associated with regulating the output voltage. the symbol, figure 30. soft pin current sources for fast and slow slew rates c soft soft isl6262 i ss + v ref i 2 + error amplifier isl6262
19 fn9199.2 may 15, 2006 slewrate, as given in the imvp-6 specification will determine the choice of the soft capacitor, c soft , by the following equation: using a slewrate of 10mv/s, and the typical i gv value, given in the electrical specification table of 200a, c soft is a choice of 0.015f would guarantee a slewrate of 10mv/s is met for minimum i gv value, given in the electrical specification table. this choice of c soft will then control the start-up slewrate as well. one should expect the output voltage to slew to the boot value of 1.2v at a rate given by the following equation: selecting rbias to properly bias the isl6262, a reference current is established by placing a 147k , 1% tolerance resistor from the rbias pin to ground. this will provide a highly accurate, 10a current source from which ocset reference current can be derived. care should be taken in layout that the resistor is placed very close to the rbias pin and that a good quality signal ground is connected to the opposite side of the rbias resistor. do not connect any other components to this pin as this would negatively impact performance. capacitance on this pin would create instabilities and should be avoided. start-up operation - clk_en# and pgood the isl6262 provides a 3.3v l ogic output pin for clk_en#. the 3v3 pin allows for a system 3.3v source to be connected to separated circuitry inside the isl6262, solely devoted to the clk_en# function. the output is a 3.3v cmos signal with 4ma sourcing and sinking capability. this implementation removes the need for an external pull-up resistor on this pin, and due to the normal level of this signal being a low, removes the leakage path from the 3.3v supply to ground through the pull-up re sistor. this reduces 3.3v supply current, that would occur under normal operation with a pull-up resistor, and prolongs battery life. the 3.3v supply should be decoupled to digital ground, not to analog ground for noise immunity. as mentioned in the ?theory of operation? section of this datasheet, clk_en# is logic level high at start-up until 20s after the system vccp and vcc_mch supplies are within regulation, and the vcc-core is in regulation at the boot level. approximately 20s after these voltages are within regulation, as indicated by pgd_in going high, clk_en# goes low, triggering an internal timer for the imvp-6_pwrgd signal. this timer allows imvp-6_pwrgd to go high approximately 6.8ms after clk_en# goes low. static mode of operatio n - processor die sensing die sensing is the ability of the controller to regulate the core output voltage at a remotely sensed point. this allows the voltage regulator to compensate for various resistive drops in the power path and ensure that the voltage seen at the cpu die is the correct level independent of load current. the vsen and rtn pins of the isl6262 are connected to kelvin sense leads at the die of the processor through the processor socket. these signal names are vcc_sense and vss_sense respectively. this allows the voltage regulator to tightly control the processor vo ltage at the die, independent of layout inconsistencies and voltage drops. this kelvin sense technique provides for extremely tight load line regulation. these traces should be laid out as noise sensitive traces. for optimum load line regulation performance, the traces connecting these two pins to the kelvin sense leads of the processor must be laid out away from rapidly rising voltage nodes, (switching nodes) and other noisy traces. to achieve optimum performance, place common mode and differential mode rc filters to analog ground on vsen and rtn as shown in figure 31. the filter resistors should be 10 so that they do not interact with the 50k input resistance of the differential amplifier. the filter resistor may be inserted between vcc_sense and vsen pin. another option is to place to the filter resistor between vcc_sense and vsen pin and between vss_sense and rtn pin. whether to need these rc filter really depends on the actual board layout and noise environment. due to the fact that the voltage feedback to the switching regulator is sensed at the proc essor die, there exists the potential of an overvoltage due to an open circuited feedback signal, should the regulator be operated without the processor installed. due to this fact, we recommend the use of the ropn1 and ropn2 connected to vout and ground as shown in figure 31. these resistors will provide voltage feedback in the event that the system is powered up without a processor installed. these resistors may typically range from 20 to 100 . c soft i gv slewrate ----------------------------------- - = (eq. 1) (eq. 2) c soft 200 a10mv1 s ? () ? = (eq. 3) dv dt ------- i ss c soft ------------------- 41 a 0.015 f ---------------------- - 2.8mv s ? == = isl6262
20 fn9199.2 may 15, 2006 setting the switching frequency - fset the r 3 modulator scheme is not a fixed frequency pwm architecture. the switching frequency can increase during the application of a load to improve transient performance. it also varies slightly due c hanges in input and output voltage and output current, but this va riation is normally less than 10% in continuous conduction mode. refer to figure 26, the resistor connected between the vw and comp pins of the is l6262 adjusts the switching window, and therefore adjusts the switching frequency. the r fset resistor that sets up th e switching frequency of the converter operating in ccm can be determined using the following relationship, where r fset is in k and the switching period is in s. place a 47pf capacitor in parallel with the frequency set resistor for better noise immunity. in discontinuous conduction mode (dcm), the isl6262 runs in period stretching mode. the switching frequency is dependent on the load current level. in general, the lighter load, the slower switching frequency. therefore, the switching loss is much reduced for the light load operation, which is important for conserving the battery power in the portable application. voltage regulator thermal throttling lntel? imvp-6 technology supports thermal throttling of the processor to prevent catastrophic thermal damage to the voltage regulator. the isl6262 features a thermal monitor which senses the voltage change across an externally placed negative temperature coefficient (ntc) thermistor. proper selection and placemen t of the ntc thermistor allows for detection of a designated temperature rise by the system. figure 32 shows the thermal throttling feature with hysteresis. at low temperature, sw1 is on and sw2 connects to the 1.18v side. the total current going into ntc pin is 60a. the voltage on ntc pin is higher than threshold voltage of 1.18v and the compar ator output is low. vr_tt# is pulling up high by the external resistor. figure 31. simplified schematic for droop and die sensing with inductor dcr current sensing c bulk esr vsum vsum vo' vo' v out i phase1 i phase2 rs rs r o2 ro1 internal to isl6262 1 + - rtn vsum dfb vo' vdiff vsen oc + - ocset 1 + - + + droop 10a droop + - vo' vo' r ocset vsum r drp2 r drp1 cn r par r ntc isen1 isen2 isen2 isen1 vdcr 1 l 1 dcr + - vdcr 2 l 2 dcr + - isen2 r l2 c l2 isen1 r l1 c l1 vcc_sense vss_sense 10 82nf 0.018f to processor socket kelvin connections r opn1 r opn2 to v out 0.018f r series (eq. 4) r fset k () period s () 0.5 ? () 1.56 ? ? figure 32. circuitry associated with the thermal throttling feature in isl6262 ntc r ntc - + v ntc - + vr_tt# 1.20v 54a internal to isl6262 r s 6a 1.18v sw1 sw2 isl6262
21 fn9199.2 may 15, 2006 when temperature increases, the ntc resistor value on ntc pin decreases. thus, the voltage on ntc pin decreases to a level lower than 1.18v. the comparator output changes polarity and turns sw1 off and connects sw2 to 1.20v. this pulls vr_tt# low and sends the signal to start thermal throttle. there is a 6a current reduction on ntc pin and 20mv voltage increase on threshold voltage of the comparator in this state. the vr_tt# signal will be used to change the cpu operation and decrease the power consumption. when the tem perature goes down, the ntc thermistor voltage will eventually go up. the ntc pin voltage increases to 1.20v, the compar ator output will then be able to flip back. such a temper ature hysteresis feature of vr_tt# is illustrated in figure 33. t 1 represents the higher temperature point at which the vr_tt# goes from low to high due to the system temperature rise. t 2 represents the lower temperature point at which the vr_tt# goes high from low because the system te mperature decreases to the normal level. usually, the ntc thermistor's resistance can be approximated by the following formula: t is the temperature of the ntc thermistor and b is a parameter constant depending on the thermistor material. t o is the reference temperatur e in which the approximation is derived. most common temperature for t o is 25c. for example, there are commercia l ntc thermistor products with b = 2750k, b = 2600k, b = 4500k or b = 4250k. from the operation principle of the vr_tt# circuit explained, the ntc resistor satisfies the following equation group. from equation 6 and equation 7, the following can be derived, using equation 5 into equation 8, the required nominal ntc resistor value can be obtained by: for some cases, the constant b is not accurate enough to approximate the ntc resistor value, the manufacturer provides the resistor ratio information at different temperature. the nominal ntc resistor value may be expressed in another way as follows: where is the normalized ntc resistance to its nominal value. most datasheet of the ntc thermistor gives the normalized resistor value based on its value at 25c. once the ntc thermistor resistor is determined, the series resistor can be derived by: once r ntcto and r s is designed, the actual ntc resistance at t 2 and the actual t 2 temperature can be found in: one example of using equations 9, 10 and 11 to design a thermal throttling circuit wit h the temperatur e hysteresis 100c to 105c is illustrated as follows. since t 1 = 105c and t 2 = 100c, if we use a panasonic ntc with b = 4700, the equation 9 gives the required ntc nominal resistance as in fact, the datasheet gives the resistor ratio value at 100c to 105c, which is 0.03956 and 0.03322 respectively. the b value 4700k in panasonic datasheet only covers to 85c. therefore, using equation 10 is more accurate for 100c design, the required ntc nominal resistance at 25c is 402k . the closest ntc resistor value from manufacturer is 470k . so the series resistance is given by equation 11 as follows, furthermore, the ntc resistance at t 2 is given by equation 12. from the ntc datasheet, it can be concluded that the actual temperature t 2 is about 97c. if using the equation 13, t 2 is calculated to be 97.7c. check the ntc datasheet to decide t 1 t 2 logic_0 logic_1 vr_tt# t (c) figure 33. temperature hysteresis of vr_tt# (eq. 5) r ntc t () r ntcto e ? = b 1 t 273 + ------------------- - 1 to 273 + ----------------------- ? ?? ?? ? (eq. 6) r ntc t 1 () r s + 1.18v 60 a --------------- - 19.67k == (eq. 7) r ntc t 2 () r s + 1.2v 54 a -------------- - 22.22k == (eq. 8) r ntc t 2 () r ntc t 1 () ? 2.55k = (eq. 9) r ntcto 2.55k e b 1 t o 273 + ----------------------- ?? ?? ? ? e b 1 t 2 273 + ----------------------- ?? ?? ? e ? b 1 t 1 273 + ----------------------- ?? ?? ? ----------------------------------------------------------------------------- - = (eq. 10) r ntcto 2.55k r ntc t 2 ? r ntc t 1 ? ? ---------------------------------------------------------------------- - = r ntc t ? (eq. 11) r s 1.18v 60 a --------------- - r ntc t1 () 19.67k r ntc_t 1 ? = ? = (eq. 12) r ntc_t 2 2.55k r ntc_t 1 + = (eq. 13) t 2_actual 1 1 b -- - r ntc_t 2 r ntcto ------------------------- ?? ?? ?? 1 273 to + () ? + ln ----------------------------------------------------------------------------------- 273 ? = r ntc_to 396k = r s 19.67k r ntc_105 c 19.67k 15.65k 4.067k = ? = ? = r ntc_t2 2.55k r ntc_t1 + 18.16k == isl6262
22 fn9199.2 may 15, 2006 whether equation 9 or equation 10 can accurately represent the ntc resistor value at the designed temperature range. therefore, the ntc branch is designed to have a 470k ntc and 4.02k resistor in series. the part number of the ntc thermistor is ertj0ev474j. it is a 0402 package. the ntc thermistor should be placed in the spot which gives the best indication of the temperature of voltage regulator circuit. the actual hysteresis temperatur e is about 105c and 97c. static mode of operation - static droop using dcr sensing as previously mentioned, the isl6262 has an internal differential amplifier which provides for very accurate voltage regulation at the die of the processor. the load line regulation is also accurate for both two-phase and single- phase operation. the process of selecting the components for the appropriate load line droop is explained here. for dcr sensing, the process of compensation for dcr resistance variation to achieve the desired load line droop has several steps and is somewhat iterative. the two-phase solution using dcr sensing is shown in figure 31. there are two resistors connecting to the terminals of inductor of each phase. these are labeled rs and ro. these resistors are used to obtain the dc voltage drop across each inductor. each inductor will have a certain level of dc current flowing through it, and this current when multiplied by the dcr of the inductor creates a small dc voltage drop across the inductor terminal. when this voltage is summed with the other channe ls dc voltages, the total dc load current can be derived. ro is typically 1 to 10 . this resistor is used to tie the outputs of all channels togethe r and thus create a summed average of the local core volt age output. rs is determined through an understanding of both the dc and transient load currents. this value will be covered in the next section. however, it is important to keep in mind that the output of each of these rs resistors are tied together to create the vsum voltage node. with both the outputs of ro and rs tied together, the simplified model for the droop circuit can be derived. this is presented in figure 34. figure 34 shows the simplified model of the droop circuitry. essentially one resistor can repl ace the ro resistors of each phase and one rs resistor can replace the rs resistors of each phase. the total dcr drop due to load current can be replaced by a dc source, the value of which is given by: for the convenience of analysis, the ntc network comprised of rntc, rseries and rpar, given in figure 31, is labelled as a single resistor rn in figure 34. the first step in droop load line compensation is to adjust rn, ro eqv and rs eqv such that sufficient droop voltage exists even at light loads between the vsum and vo' nodes. as a rule of thumb we start with the voltage drop across the rn network, vn, to be 0.5-0.8 times v dcr_equ . this ratio provides for a fairly reasonabl e amount of light load signal from which to arrive at droop. the resultant ntc network resistor value is dependent on the temperature and given by for simplicity, the gain of vn to the v dcr_equ is defined by g1, also dependent on the temperature of the ntc thermistor. (eq. 14) v dcr_equ i out dcr ? 2 -------------------------------- - = (eq. 15) r n t () r series r ntc + () r par ? r series r ntc r par ++ -------------------------------------------------------------- = internal to isl6262 1 + - rtn vsum dfb vo' vdiff vsen oc + - ocset 1 + - + + droop 10a droop + - vo' vsum rdrp2 rdrp1 cn + vn - rn rntc rseries + () rpar rntc rseries + () rpar + -------------------------------------------------------------------- = vdcr eqv i out dcr 2 ------------- = rs eqv rs 2 -------- = ro eqv ro 2 -------- - = figure 34. equivalent model for droop and die sensing using dcr sensing isl6262
23 fn9199.2 may 15, 2006 therefore, the output of the droop amplifier divided by the total load current can be expressed as follows. where r droop is the realized load line slope and 0.00393 is the temperature coefficient of the copper. to achieve the droop value independent from the temperature of the inductor, it is equivalently expressed by the following. the non-inverting droop amplifier circuit has the gain k droopamp expressed as: g 1target is the desired gain of vn over i out ? dcr/2. therefore, the temperature characteristics of gain of vn is described by: for the g 1target = 0.76, the rntc = 10k with b = 4300, rseries = 2610k , and rpar = 11k , rs eqv = 1825 generates a desired g1, close to the feature specified in equation 20. the actual g1 at 25c is 0.763. for different g1 and ntc thermistor pref erence, the design file to generate the proper value of rntc, rseries, rpar, and rs eqv is provided by intersil. then, the individual resistors from each phase to the vsum node, labeled rs1 and rs2 in figure 31, are then given by the following equation. so, rs = 3650 . once we know the attenuation of the rs and rn network, we can then determine the droop amplifier gain required to achieve the load line. setting rdrp1 = 1k_1%, then rdrp2 is can be found using equation droop impedance (rdroop) = 0.0021 (v/a) as per the intel imvp-6 specification, dcr = 0.0008 typical for a 0.36h inductor, rdrp1 = 1k and the attenuation gain (g1) = 0.77, rdrp2 is then given by note, we choose to ignore the ro resistors because they do not add significant error. these designed values in rn network are very sensitive to layout and coupling factor of th e ntc to the inductor. as only one ntc is required in this application, this ntc should be placed as close to the channel 1 inductor as possible and pcb traces sensing the inductor voltage should be go directly to the inductor pads. once the board has been laid out, some adjustments may be required to adjust the full load droop voltage. this is fairly easy and can be accomplished by allowing the system to achieve thermal equilibrium at fu ll load, and then adjusting rdrp2 to obtain the appropriate load line slope. to see whether the ntc has compensated the temperature change of the dcr, the user c an apply full load current and wait for the thermal steady state and see how much the output voltage will deviate from the initial voltage reading. a good compensation can limit the drift to 2mv. if the output voltage is decreasing with temp erature increase , that ratio between the ntc thermistor value and the rest of the resistor divider network has to be increased. the user should follow the evaluation board value and layout of ntc as much as possible to minimize engineering time. the 2.1mv/a load line should be adjusted by rdrp2 based on maximum current, not based on small current steps like 10a, as the droop gain might vary between each 10a steps. basically, if the max current is 40a, the required droop voltage is 84mv. the user should have 40a load current on and look for 84mv droop. if the drop voltage is less than 84mv, for example, 80mv. the new value will be calculated by: for the best accura cy, the effective resistance on the dfb and vsum pins should be identical so that the bias current of the droop amplifier does not cause an offset voltage. in the example above, the resist ance on the dfb pin is rdrp1 in parallel with rdrop2, that is, 1k in parallel with 5.82k or 853 . the resistance on the vsum pin is rn in parallel with rs eqv or 5.87k in parallel with 1.825k or 1392 . the mismatch in the effective resistances is 1392 - 853 = 539 . do not let the mismatch get larger than 600 . to reduce the mismatch, multiply both rdr p1 and rdrp2 by the appropriate factor. the appropriate factor in the example is 1392/853 = 1.632. in summary, the predicted load line with the designed droop network parameters based on the intersil design tool is shown in figure 35. (eq. 16) g 1 t () = r n t () r n t () rs eqv + ------------------------------------------- (eq. 17) dcr t () dcr 25 c 1 0.00393*(t-25) + () ? = (eq. 18) r droop g 1 t () dcr 25 2 ------------------- 1 0.00393*(t-25) + () k droopamp ? ? ? = (eq. 19) g 1 t () 1 0.00393*(t-25) + () g 1t et arg ? ? k droopamp 1 r drp2 r drp1 --------------- - + = (eq. 20) g 1 t () g 1t et arg 1 0.00393*(t-25) + () ------------------------------------------------------ - = (eq. 21) rs 2 rs eqv ? = (eq. 22) rdrp2 2r droop ? dcr g1 25 c () ? ----------------------------------------------- 1 ? ?? ?? r drp1 ? = rdrp2 2r droop ? 0.0008 0.763 ? -------------------------------------- - 1 ? ?? ?? 1k 5.82k ? = rdrp2_new 84mv 80mv ---------------- rdrp1 rdrp2 + () rdrp1 ? = isl6262
24 fn9199.2 may 15, 2006 dynamic mode of operation - dynamic droop using dcr sensing droop is very important for load transient performance. if the system is not compensated correctly, the output voltage could sag excessively upon load application and potentially create a system failure. the outp ut voltage could also take a long period of time to settle to its final value. this could be problematic if a load dump were to occur during this time. this situation would cause the output voltage to rise above the no load setpoint of the converter and could potentially damage the cpu. the l/dcr time constant of the inductor must be matched to the rn*cn time constant as shown in the following equation: solving for cn we now have the following equation: note, ro was neglected. as long as the inductor time constant matches the cn, rn and rs time constants as given above, the transient per formance will be optimum. as in the static droop case, this process may require a slight adjustment to correct for layout inconsistencies. for the example of l = 0.36h with 0.8m dcr, cn is calculated below. the value of this capacitor is selected to be 330nf. as the inductors tend to have 20% to 30% tolerances, this cap generally will be tuned on the board by examining the transient voltage. if the output voltage transient has an initial dip, lower than the voltage required by the load line, and slowly increases back to the steady state, the cap is too small and vice versa. it is better to have the cap value a little bigger to cover the tolerance of the inductor to prevent the output voltage from going lower than the spec. this cap needs to be a high grade cap like x7r with low tolerance. there is another consideration in order to achieve better time constant match mentioned above. the npo/cog (class-i) capacitors have only 5% tolerance and a very good thermal characteristics. but those caps are only available in small capacitance values. in order to use such capacitors, the resistors and thermistor s surrounding the droop voltage sensing and droop amplifier has to be resized up to 10x to reduce the capacitance by 10x. but attention has to be paid in balancing the impedance of droop amplifier in this case. dynamic mode of operation - compensation parameters considering the voltage regulator as a black box with a voltage source controlled by vid and a series impedance, in order to achieve the 2.1mv/a load line, the impedance needs to be 2.1m . the compensation design has to target the output impedance of th e converter to be 2.1m . there is a mathematical calculation file available to the user. the power stage parameters such as l and cs are needed as the input to calculate the co mpensation component values. attention has to be paid to the input resistor to the fb pin. too high of a resistor will caus e an error to the output voltage regulation because of bias current flowing in the fb pin. it is better to keep this resistor below 3k when using this file. static mode of operatio n - current balance using dcr or discrete resi stor current sensing current balance is achieved in the isl6262 through the matching of the voltages present on the isen pins. the isl6262 adjusts the duty cycles of each phase to maintain equal potentials on the isen pins. rl and cl around each inductor, or around each discrete current resistor, are used to create a rather large time constant such that the isen voltages have minimal ripple voltage and represent the dc current flowing through each channel's inductor. for optimum performance, rl is chosen to be 10k and cl is selected to be 0.22f. when discrete resistor sensing is used, a capacitor most likely needs to be placed in parallel with rl to properly compensate the current balance circuit. isl6262 uses rc filter to sense the average voltage on phase node and forces the average voltage on the phase node to be equal for current balance. even though the isl6262 forces the isen volta ges to be almost equal, the inductor currents will not be exactly equal. take dcr current sensing as example, two errors have to be added to find the total current imbalance. 1) mi smatch of dcr: if the dcr has a 5% tolerance then the resistors could mismatch by 10% worst case. if each phase is carrying 20a then the phase currents mismatch by 20a*10% = 2a. 2) mismatch of phase voltages/offset voltage of isen pins. the phase voltages are within 2mv of each other by current balance circuit. the error current that results is given by 2mv/dcr. if dcr = 1m then the error is 2a. 2.05 2.1 2.15 2.2 2.25 0 20406080100 inductor temperature (c) load line (mv/a) figure 35. load line performance with ntc thermal compensation (eq. 23) l dcr ------------- r n rs eqv ? r n rs eqv + ---------------------------------- c n ? = (eq. 24) c n l dcr ------------- r n rs eqv ? r n rs eqv + ---------------------------------- ---------------------------------- - = (eq. 25) c n 0.36 h 0.0008 ------------------- - parallel 5.87k, 1.825k () ------------------------------------------------------------------ 330nf = isl6262
25 fn9199.2 may 15, 2006 in the above example, the two errors add to 4a. for the two phase dc/dc, the currents would be 22a in one phase and 18a in the other phase. in t he above analysis, the current balance can be calculated with 2a/20a = 10%. this is the worst case calculation, for exam ple, the actual tolerance of two 10% dcrs is 10%*sqrt(2) = 7%. there are provisions to correct the current imbalance due to layout or to purposely divert current to certain phase for better thermal management. custom er can put a resistor in parallel with the current sens ing capacitor on the phase of interest in order to purposely increase the current in that phase. in the case the pc board trace resistance from the inductor to the microprocessor are not the same on two phases, the current will not be balanced. on the phase that have too much trace resistance a resistor can be added in parallel with the isen capacitor that will correct for the poor layout. an estimate of the value of the resistor is: rtweak = risen * rdcr/(rtrace-rmin) where risen is the resistance from the phase node to the isen pin; usually 10k . rdcr is the dcr resistance of the inductor. rtrace is the trace resistance from the inductor to the microprocessor on the phase that needs to be tweaked. it should be measured with a good microohm meter. rmin is the trace resistance from the inductor to the microprocessor on the phase with the least resistance. for example, if the pc board trace on one phase is 0.5m and on another trace is 0.3m ; and if the dcr is 1.2m ; then the tweaking resistor is rtweak = 10k * 1.2/(0.5 - 0.3) = 60k . when choosing current sense resi stor, not only the tolerance of the resistance is important, but also the tcr. and its combined tolerance at a wide temperature range should be calculated. droop using discrete resistor sensing - static/ dynamic mode of operation figure 36 shows the equivalent circuit of a discrete current sense approach. figure 27 shows a more detailed schematic of this approach. dr oop is solved the same way as the dcr sensing approach with a few slight modifications. first, there is no ntc required for thermal compensation, therefore, the rn resistor netw ork in the previous section is not required. secondly, there is no time constant matching required, therefore, the cn co mponent is not matched to the l/dcr time constant. this co mponent does indeed provide noise immunity and therefore is populated with a 39pf capacitor. the rs values in the previous section, rs = 1.5k_1% are sufficient for this approach. now, the input to the droop amplifier is essentially the vrsense voltage. this voltage is given by the following equation: the gain of the droop amplifier, k droopamp , must be adjusted for the ratio of the rsense to droop impedance, rdroop. we use the following equation: solving for the rdrp2 value, rdroop = 0.0021(v/a) as per the intel imvp-6 specific ation, rsense = 0.001 and rdrp1 = 1k , we obtain the following: these values are extremely sensitive to layout. once the board has been laid out, some tweaking may be required to adjust the full load droop. th is is fairly easy and can be accomplished by allowing the system to achieve thermal equilibrium at full load, and then adjusting rdrp2 to obtain the desired droop value. fault protection - overcurrent fault setting as previously described, the ov ercurrent protection of the isl6262 is related to the droop voltage. previously we have calculated that the droop volt age = iload * rdroop, where rdroop is the load line slope specified as 0.0021 (v/a) in the intel imvp-6 specification. kn owing this relationship, the overcurrent protection threshold can be set up as a voltage droop level. knowing this voltage droop level, one can program in the appropriate drop across the roc resistor. this voltage drop will be referred to as voc. once the droop voltage is greater than voc, the pwm drives will turn off and pgood will go low. the selection of roc is given in equation. assuming we desire an overcurrent trip level, ioc, of 55a, and knowing from the intel specification that the load line slope, rdroop is 0.0021 (v/a), we can then calculate for roc as shown in equation. note, if the droop load line sl ope is not -0.0021 (v/a) in the application, the overcurrent setpoint will differ from predicted. (eq. 26) vrsense eqv r sense 2 ------------------- - i out ? = (eq. 27) k droopamp r droop r sense ------------------- - i out ? = (eq. 28) rdrp2 k droopamp 1 ? () r drp1 ? 3.2k = = (eq. 29) r oc i oc r droop ? 10 a ----------------------------------- 55 0.0021 ? 10 10 6 ? ? ------------------------------ 11.5k === isl6262
26 fn9199.2 may 15, 2006 internal to isl6262 1 + - rtn vsum dfb vo' vdiff vsen oc + - ocset 1 + - + + droop 10a droop + - vo' vsum rdrp2 rdrp1 cn + vn - vrsense eqv i out rsense 2 ---------------------- = rs eqv rs 2 -------- = ro eqv ro 2 -------- - = figure 36. equivalent model for droop and di e sensing using discrete resistor sensing roc voc + - isl6262
27 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn9199.2 may 15, 2006 isl6262 quad flat no-lead plastic package (qfn) micro lead frame pl astic package (mlfp) index d/2 d e/2 e a b c 0.10 b a mc n seating plane n 6 3 2 2 3 e 1 1 section "c-c" nx b a1 2x c 0.15 0.15 2x b ref. (nd-1)xe (ne-1)xe ref. 5 a c d2 d2 e2 side view top view 7 bottom view 7 5 2 nx k nx b 8 nx l 8 8 area (datum b) (datum a) area index 6 area n a 0.08 a1 c a3 0.10 c / / e2/2 l48.7x7 48 lead quad flat no-lead plastic package (compliant to jedec mo-220vkkd-2 issue c) symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 - - 0.05 - a3 0.20 ref - b 0.18 0.23 0.30 5, 8 d 7.00 bsc - d2 4.15 4.30 4.45 7, 8 e 7.00 bsc - e2 4.15 4.30 4.45 7, 8 e 0.50 bsc - k0.25 - - - l 0.30 0.40 0.50 8 n482 nd 12 3 ne 12 3 rev. 2 5/06 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on each d and e. 4. all dimensions are in millimeters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are provided to assist with pcb land pattern design efforts, see intersil technical brief tb389.

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